VSC8115
Data Sheet
STS-12/STS-3 Multirate Clock and Data Recovery Unit
F
EATURES
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Performs Clock and Data Recovery for
622.08Mb/s (STS-12/OC-12/STM-4) or
155.52Mb/s (STS-3/OC-3/STM-1) NRZ Data
19.44MHz Reference Frequency LVTTL Input
Lock Detect Output Pin Monitors Data Run
Length and Frequency Drift from Reference Clock
Data is Retimed at the Output
Active HIGH Signal Detect LVPECL Input
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Low Jitter, High-Speed Outputs Can Be Config-
ured as either LVPECL or Low Power LVDS
Low Power: 188mW Typical Power
+3.3V Power Supply
20-Pin TSSOP Package
Requires One External Capacitor
PLL Bypass Operation Facilitates Board Debug
Process
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G
ENERAL
D
ESCRIPTION
The VSC8115 functions as a Clock and Data Recovery (CDR) unit for SONET/SDH-based equipment to derive high-
speed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s (STS-
12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed using an
output flip-flop. Both recovered clock and retimed data outputs can be configured as LVDS or LVPECL signals to
facilitate a low-jitter and low-power interface.
VSC8115 Block Diagram
STS12
Divider
CAP+
Loop
Filter
CAP–
VCO
LOCKDET
2
DATAOUT±
BYPASS
2
DATAIN±
SD
LOCKREFN
REFCLK
Phase/
Frequency
Detector
0
1
2
CLKOUT±
G52272, Rev 4.2
5/14/03
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VITESSE SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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