VSC8115
Data Sheet
Jitter Generation
Jitter generation is defined as the jitter of the serial clock and serial data outputs, while rms jitter is presented to the
serial data inputs. Maximum jitter generation is 0.01 UI when rms jitter of less than 14ps (OC-12) or 56ps (OC-3) is
presented to the serial data inputs.
Retimed Data and Clock Outputs
It is recommended that the retimed data output be captured with the rising edge of the clock output as shown in
Figure 3.
Data valid time is longer for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data valid time
before the output clock’s rising edge is the available setup time (t
SU
), while the data valid time after the clock’s rising
edge is the available hold time (t
H
).
DATAOUT+
CLKOUT+
t
SU
t
H
Figure 3. Retimed Data and Clock Outputs Timing Diagram
Table 11. Retimed Data and Clock Outputs Timing
Symbol
t
SU
t
H
Parameter
Available Setup Time
Available Hold Time
Min
450
2.0
650
3.0
Typ
Max
Units
ps
ns
ps
ns
Condition
STS-12 operation (622.08MHz)
STS-3 operation (155.52MHz)
STS-12 operation (622.08MHz)
STS-3 operation (155.52MHz)
7 of 12
G52272, Rev 4.2
5/14/03
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
