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VSC8115YA-03 参数 Datasheet PDF下载

VSC8115YA-03图片预览
型号: VSC8115YA-03
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Recovery Circuit, 1-Func, PDSO20, 4.40 X 6.50 MM, TSSOP-20]
分类和应用: ATM异步传输模式电信光电二极管电信集成电路
文件页数/大小: 12 页 / 549 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC8115  
Data Sheet  
AC CHARACTERISTICS  
Over Recommended Operating Conditions.  
Table 10. Performance Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Units Condition  
f
VCO Center Frequency  
622.08  
MHz  
ppm  
f
CRUs Reference Clock Frequency  
250  
+250  
TOL  
Tolerance  
fT  
OC-12/STS-12 Capture Range  
500  
ppm  
With respect to the fixed  
reference frequency.  
% of UI 20% minimum transition density.  
REF_CLK  
CLKOUT  
Clock Output Duty Cycle  
45  
55  
16  
DC  
t
OC-12/STS-12 Acquistion Lock Time  
µs  
Valid REFCLK and device  
already powered up.  
LOCK  
t
t
,
LVDS and LVPECL Output Rise and  
Fall Times  
500  
ps  
10% to 90%, with 100 and 5pF  
capacitive equivalent load.  
LOCKDET_R  
LOCKDET_F  
J
J
CLKOUT Jitter Generation  
0.005  
0.01  
UI  
UI  
GEN_CLK  
OC-12/STS-12 Jitter Tolerance  
0.45  
Sinusoidal input jitter of  
TOL  
DATAIN from 250kHz to 5MHz.  
Jitter Tolerance  
Jitter tolerance is the ability of the CDR to track timing variations in the received data stream. The Bellcore and ITU  
specifications allow the received optical data to contain jitter, however, the amount that must be tolerated is a function  
of the frequency of the jitter. At high frequencies the specifications do not require the VSC8115 to tolerate large  
amounts of jitter, whereas, at low frequencies, many unit intervals (bit times) of jitter have to be tolerated. Jitter  
tolerance is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/  
STS-N signal versus frequency. The VSC8115 is designed to tolerate this jitter with margin over the specification  
limits. See Figure 2. The VSC8115 obtains and maintains lock based on the data transition information. When there is  
no transition on the data stream, the recovered clock frequency will be held to within 500ppm of the reference clock.  
The VSC8115 can maintain lock status with a data stream carrying over 1,000 consecutive identical digits (CID).  
150  
Bellcore Requirement  
15  
1.5  
0.15  
0
0
10  
30  
300  
25k  
250k  
2.5M  
Jitter Frequency (Hz)  
Figure 2. Input Jitter Tolerance Specification  
6 of 12  
G52272, Rev 4.2  
5/14/03  
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