VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Figure 13: VSC8026 Functional Timing Diagram (STS-48 Mode)
RXSCLKIN
RXSIN
DD1 DD1 DD1 DD1 DD1 DD1 DD1 DD1
b7 b6 b5 b4 b3 b2 b1 b0
RXPCLKIN
RXPIN[7:0]
RXFPIN
Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 DA1 DA2 DA3 DA4 DB1 DB2 DB3 DB4 DC1 DC2 DC3 DC4 DD1 DD2 DD3 DD4 DA5 DA6 DA7 DA8 DB5 DB6 DB7 DB8
RXCLKOUTA
RXCLKOUTB
RXOUTA[7:0]
RXOUTB[7:0]
RXOUTC[7:0]
RXOUTD[7:0]
RXFPOUT
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
DA1
DB1
DC1
DD1
DA2
DB2
DC2
DD2
DA3
DB3
DC3
DD3
DA4
DB4
DC4
DD4
DA5
DB5
DC5
DD5
RXFRERR
RXSEF
Note:
(1) The correct latency between RXPIN, RXSIN and RXOUTA-D is NOT shown.
(2) RXPIN is equivalent to RXSIN (byte wide) in normal operation (EQULOOP low). RXFPIN is not applicable in normal
operation.
Figure 14: VSC8026 Functional Timing (B1ERR output)
RXCLKOUTA
RXCLKOUTB
RXOUTA[7:0]
B1ERR
DA1041 DA1042 DA1043 DA1044
B1
Unused Unused Unused Unused
G52182-0, Rev. 4.0
VITESSE SEMICONDUCTOR CORPORATION
Page 23
1/5/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896