VITESSE
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
SEMICONDUCTOR CORPORATION
Datasheet
VSC8025/VSC8026
lel input port RXPIN[7:0]. In this mode of operation, the internal clock source is RXPCLKIN, rather than the
divide-by-8 clock generated by the 1:8 Demux. The parallel input is also equipped with a frame pulse input
RXFPIN, which can be used for synchronizing the internal frame counter when the frame detection circuit is
disabled, which might be desirable if the VSC8026 is used in a STS-192/STM-64 setup. Data on RXPIN[7:0]
and RXFPIN are captured on the falling edge of RXPCLKIN+ (refer to Figure 18).
Facility Loopback
To create a facility (or line) loopback the registered RXSIN data and the RXSCLKIN are brought out of the
chip (RXSLBOUT and RXSLBCLK). These two signals should be connected to the TXSLBIN and TXSLB-
CLK inputs on the VSC8025 to create a facility loopback. RXSLBOUT and RXSLBCLK outputs are added to
minimize the loading on the high speed clock and data lines coming from the RX optics module. To minimize
jitter on RXSIN and RXSCLKIN inputs during normal operation, the RXSLBOUT and RXSLBCLK outputs
can be disabled by holding the asynchronous FACLOOP input low. Please refer to Figure 21 for a detailed facil-
ity loopback circuit diagram.
STS-48c Mode
To support STS-48c operation, where bytes from the four STS-12/STM-4 inputs are interleaved on at a time
(as opposed to four at a time in STS-48 mode), the byte interleaver can be configured for STS-48c multiplexing
by holding the asynchronous SELSTS48C input high.
Descrambler
The VSC8026 performs optional descrambling using a frame synchronous descrambler with generating
6
7
polynomial 1 + x + x and a sequence length of 127. The descrambler is disabled by asserting DISDSCRM
high. DISDSCRM is latched-in once every frame.
Error Performance (B1)
The section bit-interleaved parity (BIP-8) error detection code B1 will be calculated for every frame before
descrambling, and compared to its extracted value after descrambling in the following frame. The B1 errors will
be presented on the B1ERR output as 25.72 ns wide pulses (up to 8 per frame). The first pulse will be aligned
with the B1 byte of the current frame (refer to Figure 14). Besides calculating the BIP-8 over the entire STS-48/
STM-16 frame, the VSC8026 also calculates a BIP-8 over the first STS-12/STM-4 frame interleaved into the
STS-48/STM-16 frame. This calculated B1
is XORed with the error-mask derived from XORing the
STS-12#1
extracted B1
with the calculated B1
over the entire STS-48/STM-16 frame. The result is inserted
STS-48
STS-48
into the B1 byte position of the first outgoing STS-12 data stream (on RXOUTA[7:0]), when the asynchronous
PROPB1ERR is held high. This will make the B1 error count on the B1ERR output identical to the B1 error
count in the first STS-12/STM-4 channel, which can be easily monitored through the microprocessor interface
of the PM5355/PM5312s.
Loss of Signal
A Loss Of Signal (LOS) input is provided to prevent random data from propagating downstream during a
LOS condition. Random data will be clocked into the VSC8026 in the absence of alternating input data, if ac-
coupling is applied between the optics module and the RXSIN input. Also, during a LOS condition, the internal
clock source is switched over to the parallel input clock RXPCLKIN, since the high speed clock (RXSCLKIN)
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VITESSE SEMICONDUCTOR CORPORATION
G52182-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/5/00
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