VITESSE
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
SEMICONDUCTOR CORPORATION
Datasheet
VSC8025/VSC8026
Parameter
Description
Min
Typ
Max
Units
Delay from falling edge of RXCLKOUT[A:D] to valid
data on RXOUTA[7:0], RXOUTB [7:0], RXOUTC
[7:0], RXOUTD[7:0], RXFPOUT, RXFRERR, RXSEF,
RXLOF, B1ERR, and RXOUT[A:D]P
TRXPOUT
-2.7
-
-
-
+0.7
0.65
ns
ns
TCSKEW
RXCLKOUT[A:D] rising edge clock skew
Figure 19: VSC8026 Parallel Data Output Timing Diagram
TRXCLKOUT
RXCLKOUTA
RXCLKOUTB
RXCLKOUTC
RXCLKOUTD
TRXPOUT
RXOUT[A:D][7:0]
RXFPOUT
RXFRERR
RXSEF
RXLOF
B1ERR
RXOUT[A:D]P
Note: (1) The TRXPOUT timing parameter is relative to both RXCLKOUTA and RXCLKOUTB.
(2) Duty cycle for RXCLKOUT[A:D] is 50% ± 10% when configured for serial input mode (EQULOOP=Ø)
Table 14: VSC8026 Serial Data Output Timing (Facility Loopback)
Parameter
Description
Serial loopback clock period
Min
Typ
Max
Units
TRXSLBCLK
-
401.9
-
ps
Delay from falling edge of RXSLBOUT+ to data
transition edge of RXSLBOUT
TRXSLBOUT
-10
-
170
ps
Figure 20: VSC8026 Serial Data Output Timing Diagram (Facility Loopback)
TRXSLBCLK
RXSLBCLK+
RXSLBCLK-
TRXSLBOUT
RXSLBOUT+
RXSLBOUT-
Page 26
VITESSE SEMICONDUCTOR CORPORATION
G52182-0, Rev. 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
