VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
might be absent during LOS (depending on the CRU used). Switching over to RXPCLKIN during LOS prevents
the VSC8026 from ‘freezing’ in the absence of a serial input clock.
Framer
The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame
is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after sys-
tem reset or if for some reason the receiver looses synchronization, e.g. due to ‘bit slips’. In-frame is defined as
a state where the frame boundaries are known.
The frame boundary detection/verification is based on either 12, 24 or 48 bits of the A1/A2 overhead as
shown in Figure 11, based on the SELFRDET[1:0] settings shown in Table 10. Frame acquisition is initiated
when FRDETEN is held high. This control is level sensitive and the VSC8026 will continually perform frame
acquisition as long as FRDETEN is held high. A functional block diagram of the frame acquisition circuit is
shown in Figure 12.
While in-frame (FRDETEN low), the receiver monitors the frame synchronization by checking the framing
pattern in each frame. If one or more bit errors are detected in the framing pattern, FRERR will be asserted for
25.72 ns (refer to Figure 13). If framing pattern errors are detected for four consecutive frames, a Severely
Errored Frame (SEF) alarm will be declared (RXSEF). The SEF alarm is terminated when two consecutive
frames with error free framing patterns have been detected.
A frame detect based on 24 bits will result in a SEF (Severely Errored Frame) alarm at an average of no
-3
more than once every 6 minutes assuming a BER of 10 as specified by the SONET Bellcore spec. A frame
detect based on 48 or 12 bits will result in a mean time between SEF detects of 0.43 and 103 minutes, respec-
tively. The frame detection circuit can be disabled by holding both asynchronous SELFRDET[1:0] inputs high.
To achieve SONET/SDH specifications for framing, the user needs to connect the RXSEF output to the FRDE-
TEN input.
Loss of Frame
A Loss Of Frame (LOF) alarm is declared (RXLOF) when a Severely Errored Frame (SEF) condition per-
sists for 3 ms. The LOF state detection is based on an integrating timer. To provide for the case of intermittent
SEF’s, the integrating timer is not reset until an in-frame condition (SEF low) persists continuously for 3 ms.
Once in a LOF state, this state is terminated when the in-frame condition persists continuously for 3 ms.
Parity
Even parity is provided for each byte wide data bus on outputs RXOUT[A:D]P; the parity calculation
includes the frame pulse if FPPAREN is logic 1. The even parity output for a bus is a logic 1 when an odd num-
ber of bits in the byte wide data and frame pulse (if FPPAREN is logic 1) are logic 1; otherwise, it is logic 0.
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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