VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Table 11: VSC8026 Serial Data Input Timing
Parameter
Description
Serial Receive clock period
Min
Typ
Max
Units
TRXSCLKIN
-
401.9
-
ps
Serial Receive input data RXSIN setup time with respect
to rising edge of RXSCLKIN+
TRXSSU
TRXSH
120
60
-
-
-
-
ps
ps
Serial Receive input data RXSIN hold time with respect
to rising edge of RXSCLKIN+
Figure 17: VSC8026 Serial Data Input Timing Diagram
TRXSCLKIN
RXSCLKIN+
RXSCLKIN-
TRXSSU TRXSH
RXSIN+
RXSIN-
Table 12: VSC8026 Parallel Data Input Timing
Parameter
Description
Parallel Receive clock period
Min
Typ
Max
Units
TRXPCLKIN
-
3.215
-
ns
Parallel Receive input data RXPIN[7:0]/RXFPIN setup
time with respect to falling edge of RXPCLKIN+
TRXPSU
TRXPH
0.0
0.8
-
-
-
-
ns
ns
Parallel Receive input data RXPIN[7:0]/RXFPIN hold
time with respect to falling edge of RXPCLKIN+
Figure 18: VSC8026 Parallel Data Input Timing Diagram (Equipment Loopback)
TRXPCLKIN
RXPCLKIN-
RXPCLKIN+
TRXPSU TRXPH
RXPIN[7:0]
RXFPIN
Table 13: VSC8026 Parallel Data Output Timing
Parameter
Description
Min
Typ
Max
Units
TRXCLKOUT
Receive data output clock period
-
12.86
-
ns
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 25
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