VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Table 9: Pin Identification Table
Signal
Pin
I/O
Level
Pin Description
RCLK155-
FACLOOP
DISFPCHK
VCC
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
R01
R02
R03
R04
R05
O
ECL
TTL
TTL
GND
-2V
Divide by 16 clock output for external CMU
Facility loop back enable (active high)
Disable frame pulse check (active high)
Ground
I
I
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I
VTT
-2.0V power supply
VDD
+3.3V
-2V
+3.3V power supply
VTT
-2.0V power supply
VTT
-2V
-2.0V power supply
VTTL
+3.3V
-2V
+3.3V power supply
VTT
-2.0V power supply
VCC
GND
TTL
TTL
ECL
GND
ECL
TTL
TTL
TTL
ECL
Ground
TXINA1
TXINA3
TESTAC7
VCC
Parallel input bus data A
Parallel input bus data A
Test pin (leave open)
I
O
PWR
O
Ground
RCLK155+
TEST 22
RESET
TESTAC5
TXPCLKOUT+
Divide by 16 clock output for external PLL
Test pin (tie to 0V)
I
I
Reset (active high)
I
Test pin (tie to 0V)
O
Parallel transmit clock out
Serial loopback clock termination. If AC coupling,
connect to GND with a decoupling capacitor. If DC
coupling, connect to Vtt directly.
TXSLBCKREF
R06
VCC
TXFPOUT
TXPOUT0
VCC
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
T01
T02
T03
T04
T05
PWR
GND
ECL
ECL
GND
ECL
ECL
TTL
TTL
TTL
TTL
TTL
TTL
GND
ECL
TTL
Ground
O
Parallel transmit frame pulse out
Parallel transmit data out
Ground
O
PWR
TXPOUT5
TXPOUT7
TESTAC6
TXINA0
TXINA5
TXINA7
TESTAC4
SELPCLK
VCC
O
Parallel transmit data out
Parallel transmit data out
Test pin (tie to 0V)
O
I
I
Parallel input bus data A
Parallel input bus data A
Parallel input bus data A
Test pin (tie to 0V)
I
I
I
I
PWR
O
Select parallel clock (active high)
Ground
TXPCLKOUT-
TSYNC
Parallel transmit clock out
I
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 17
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