VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
VSC8025/VSC8026
Mux/Demux and Section Terminator IC Chipset
Table 9: Pin Identification Table
Signal
Pin
I/O
Level
Pin Description
VTTL
VCC
K14
K15
K16
L01
L02
L03
L04
L13
L14
L15
L16
M01
M02
M03
M04
M13
M14
M15
M16
PWR
PWR
I
+3.3V
GND
3.3V power supply
Ground
TXINB6
TXSCLKOUT-
N/C
TTL
Parallel input bus data B
High-speed serial clock out
No connection (leave open)
Serial loop back input
-2.0V power supply
-2.0V power supply
Parallel input bus data B
Parallel input bus data B
Parallel input bus data B
No connection (leave open)
Serial loop back input
Ground
O
HSECL
TXSLBIN-
VTT
I
HSECL
-2V
PWR
VTT
PWR
-2V
TXINB1
TXINB3
TXINB5
N/C
I
I
I
TTL
TTL
TTL
TXSLBIN+
VCC
I
HSECL
GND
+3.3V
+3.3V
GND
TTL
PWR
PWR
PWR
PWR
I
VTTL
+3.3V power supply
+3.3V power supply
Ground
VTTL
VCC
TXINB2
TXINB4
Parallel input bus data B
Parallel input bus data B
I
TTL
Serial loopback data termination. If AC coupling, connect
to GND with a decoupling capacitor. If DC coupling,
connect to Vtt directly.
TXSLBINREF
N01
N/C
VCC
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
P01
No connection (leave open)
Ground
PWR
I
GND
TTL
TEST 23
SELSTS48C
VCC
Test pin (tie to 0V)
STS-48c mode (active high)
Ground
I
TTL
PWR
PWR
PWR
PWR
PWR
PWR
I
GND
+3.3V
GND
GND
GND
GND
TTL
VDD
+3.3V power supply
Ground
VCC
VCC
Ground
VCC
Ground
VCC
Ground
TXINA2
TXINA4
VCC
Parallel input bus data A
Parallel input bus data A
Ground
I
TTL
PWR
I
GND
TTL
TXFPINB
TXINB0
VCC
Transmit frame pulse in (active high)
Parallel input bus data B
Ground
I
TTL
PWR
GND
Page 16
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52182-0, Rev. 4.0
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
