VSC6134
Datasheet
Table 458. Microprocessor Interface Pins (continued)
Pin
Name
I/O Type
Description
H2
SYNSEL_DSN_WRN
TI
Motorola Mode:
Microprocessor synchronous mode select. SYNSEL
signal selects between the Pseudo-Synchronous and
Synchronous modes.
Intel Mode:
Microprocessor Synchronous mode select. In the
Synchronous mode, the SYNSEL signal must be tied
high.
Microprocessor write strobe. In the Asynchronous
mode, the WRN signal is low during a write access.
H4
RWN_WRN_RDN
TI
Motorola Mode:
Microprocessor read/write selection. In the
Synchronous mode, the RWN signal is high for a read
operation and low for a write operation.
Intel Mode:
Microprocessor write/read selection. WRN signal is
high for a write operation and low for a read operation.
Microprocessor write strobe. In the Asynchronous
mode, the RDN signal is low during a read access. The
device drives the data bus MPDATA[15:0] when both
CSN and RDN are low.
J1
DTKN_RDYN_RDY
TO
Motorola Mode:
Microprocessor data acknowledge signal. DTKN is an
active low data acknowledgement signal. This signal is
normally tristated and makes a low to high transition
before being tristated.
Intel Mode:
Microprocessor data ready signal. RDYN is an active
low data acknowledgement signal. In the
Asynchronous mode, RDY is an active high data
acknowledgement signal.
J3
CSN
TI
TI
Microprocessor chip select. Active low signal during a
register read or write access.
K1
MPMODE
Microprocessor mode select. Must be set to 0 for Intel
asynchronous operation and to 1 for Motorola and Intel
synchronous operation.
J4
L2
MPSEL
INTN
TI
Microprocessor type select. Must be set to 0 for
Motorola type processors and to 1 for Intel type
processors.
ODO
Microprocessor interrupt. Active low, open drain signal
indicating an interrupt event. This signal remains low
until all active, unmasked interrupt sources are
cleared. External pull-up is required.
T3
L1
MPU_CLK
TI
Microprocessor clock. This clock is needed in all
modes. When MPMODE = 1, this is 50 MHz and is
synchronous to the microprocessor clock. When
MPMODE = 0, this should be a 50-MHz clock.
HW_RESETN
TIU
Active low power-up asynchronous reset. This input
has an internal pull-up resistor.
409 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
