VSC6134
Datasheet
3.8.57
DW Path Monitor Configuration Register
Address:
0xF39: Add Path
0x739: Drop Path
0x0000
Register Reset Value:
Table 258. DW Path Monitor Configuration Register
Reset
Value
Bit
Name
Access
RO
Description
15:13
12:8
Reserved
PM_TTIPNT
000
R/W
PM TTI MPU read pointer.
0x00
This is the MPU read pointer into the PM TTI FIFO that
auto-increments on an MPU read or write.
7
PM_TTIINVD
Reserved
R/W
RO
PM TTI invalidate.
A zero to one transition clears the three PM TTI live bits,
invalidating all PM TTI fields.
0
6:0
0x00
3.8.58
DW Path Monitor BIP-8 Bit Error Count Register (MSW)
Address:
0xF3A: Add Path
0x73A: Drop Path
0x0000
Register Reset Value:
Table 259. DW Path Monitor BIP-8 Bit Error Count Register (MSW)
Reset
Value
Bit
15:8
7:0
Name
Access
RO
Description
Reserved
0x00
0x00
PM_BIP8CNT[23:16]
RO
PM BIP-8 bit error counter MSW
3.8.59
DW Path Monitor BIP-8 Bit Error Count Register (LSW)
Address:
0xF3B: Add Path
0x73B: Drop Path
0x0000
Register Reset Value:
Table 260. DW Path Monitor BIP-8 Bit Error Count Register (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
PM_BIP8CNT[15:0]
RO
PM BIP-8 bit error counter LSW
0x0000
311 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
