VSC6134
Datasheet
3.8.35
DW Overhead Monitor FTFL Configuration Register
Address:
0xF22: Add Path
0x722: Drop Path
0x001F
Register Reset Value:
Table 236. DW Overhead Monitor FTFL Configuration Register
Reset
Value
Bit
15
Name
Access
RO
Description
Reserved
FTFL_MPNT
0
14:8
R/W
FTFL MPU pointer.
0x00
This is a pointer into the FTFL FIFO that auto-increments
on an MPU read or write.
7
FTFL_INVD
R/W
FTFL invalidate.
0
A zero to one transition clears the four FTFL live bits,
invalidating all FTFL fields.
6
Reserved
RO
0
5:3
FTFL_MAT
R/W
FTFL match.
011
These bits determine the consecutive number of matching
FTFL FOPI, FOPS, BOPI, or BOPS fields before setting the
respective live bits active, indicating a valid FTFL field. 0
through 7 values correspond to 1 through 8 matches.
2:0
FTFL_MIS
R/W
FTFL mismatch
111
These bits determine, when the respective live bit is active,
the consecutive number of mismatching FTFL FOPI,
FOPS, BOPI, or BOPS fields before clearing the respective
live bit. 0 through 7 values correspond to 1 through 8
mismatches.
300 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
