VSC6134
Datasheet
3.8.25
Standard FEC Corrected Bit Error Count (LSW)
Address:
0xF16: Add Path
0x716: Drop Path
0x0000
Register Reset Value:
Table 226. Standard FEC Corrected Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
TOTAL_StFEC_ERR_LWR
RO
Count of the total number of Reed Solomon decoder
correctable bit errors (lower 16 bits of 32 bit count)
0x0000
3.8.26
Standard FEC Corrected Bit Error Count (MSW)
Address:
0xF17: Add Path
0x717: Drop Path
0x0000
Register Reset Value:
Table 227. Standard FEC Corrected Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
TOTAL_StFEC_ERR_UPR
RO
Count of the total number of Reed Solomon decoder
correctable bit errors (upper 16 bits of 32 bit count)
0x0000
3.8.27
Standard FEC Early Transition Bit Error Count (LSW)
Address:
0xF18: Add Path
0x718: Drop Path
0x0000
Register Reset Value:
Table 228. Standard FEC Early Transition Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
EARLY_TX_ERR_LWR
RO
Count of Reed Solomon decoder errors where the 0-> 1 or
1-> 0 transition comes early (lower 16 bits of 32 bit count).
“Performance Monitoring,’ page 119
0x0000
297 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
