VSC6134
Datasheet
3.8.28
Standard FEC Early Transition Bit Error Count (MSW)
Address:
0xF19: Add Path
0x719: Drop Path
0x0000
Register Reset Value:
Table 229. Standard FEC Early Transition Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
EARLY_TX_ERR_UPR
RO
Count of Reed Solomon decoder errors where the 0-> 1 or
1-> 0 transition comes early (upper 16 bits of 32 bit count).
“Performance Monitoring,’ page 119
0x0000
3.8.29
Standard FEC Late Transition Bit Error Count (LSW)
Address:
0xF1A: Add Path
0x71A: Drop Path
0x0000
Register Reset Value:
Table 230. Standard FEC Late Transition Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
LATE_TX_ERR_LWR
RO
Count of Reed Solomon decoder errors where the 0-> 1 or
1-> 0 transition comes late (lower 16 bits of 32 bit count).
“Performance Monitoring,’ page 119
0x0000
3.8.30
Standard FEC Late Transition Bit Error Count (MSW)
Address:
0xF1B: Add Path
0x71B: Drop Path
0x0000
Register Reset Value:
Table 231. Standard FEC Late Transition Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
LATE_TX_ERR_UPR
RO
Count of Reed Solomon decoder errors where the 0-> 1 or
1-> 0 transition comes late (upper 16 bits of 32 bit count).
“Performance Monitoring,’ page 119
0x0000
298 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
