VSC6134
Datasheet
3.8.39
DW Overhead Monitor Configuration Register
Address:
0xF27: Add Path
0x727: Drop Path
0x5800
Register Reset Value:
Table 240. DW Overhead Monitor Configuration Register
Reset
Value
Bit
Name
Access
Description
15:13
TTI_MAT
R/W
TTI match.
011
These bits determine the consecutive number of matching
SM, TCM, and PM TTI fields before setting the respective
TTI live bits active, indicating a valid field. 0 through 7
values correspond to 1 through 8 matches.
12:10
TTI_MIS
R/W
TTI mismatch.
111
These bits determine, when the respective live bits are
active, the consecutive number of mismatching TTI fields
before clearing the respective live bits. 0 through 7 values
correspond to 1 through 8 mismatches.
9
BDI_MANU
BDISF
R/W
R/W
BDI manual.
0
A 1 forces SM, PM, and the selectively generated TCM BDI
bits high on the backwards path.
8:7
BDI signal fail.
00
These signals determine which combination of received
LOF and LOS conditions set BDI in the trasmit direction.
00: BDI is not set high
01: LOS sets BDI high.
10: LOF sets BDI high.
11: LOS or LOF set BDI high.
6:5
4
Reserved
00
0
IAE_CTRL
R/W
R/W
R/W
RO
IAE error count control.
0: Do not allow IAE to pause BIP-8 and BEI error
accumulation for SM and TCM.
1: Pause BIP-8 and BEI error accumulation for SM and
TCM when IAE is asserted.
3
2
OOFDBC_CTRL
OOFCNT_CTRL
Reserved
OOF debounce control.
0: Do not allow OOF to affect debouncing of collected
overhead data.
1: Reset debouncing and hold previous state when OOF is
asserted.
0
0
OOF error count control.
0: Do not allow OOF to pause BIP-8 and BEI error
accumulation.
1: Pause BIP-8 and BEI error accumulation when OOF is
asserted.
1:0
00
303 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
