VSC6134
Datasheet
3.8.37
DW Overhead Monitor GCC Configuration Register 1
Address:
0xF24: Add Path
0x724: Drop Path
0x0001
Register Reset Value:
Table 238. DW Overhead Monitor GCC Configuration Register 1
Reset
Value
Bit
Name
Access
Description
15:8
GCC_MPNT
R/W
GCC MPU pointer.
0x00
This is the MPU read pointer into the GCC FIFO that
auto-increments on an MPU read or write.
7:5
GCC_CFG
R/W
GCC configuration.
000
These bits determine whether GCC0, GCC1, or GCC2 are
loaded into the GCC FIFO.
000: Load nothing.
001: Load GCC0.
010: Load GCC1.
011: Load GCC0 and GCC1.
100: Load GCC2.
101: Load GCC0 and GCC2.
110: Load GCC1 and GCC2.
111: Load all GCC bytes.
4:3
2
Reserved
RO
R/W
R/W
000
0
GCC_PINGPONG
GCC_MPNTI
A zero-to-one transition ping-pongs between GCC FIFOs.
1:0
These bits determine whether the auto increment is by 1, 2,
01
or 3.
00: Reserved.
01: Increment by 1.
10: Increment by 2.
11: Increment by 3.
3.8.38
DW Overhead Monitor GCC FIFO Access Register
Address:
0xF26: Add Path
0x726: Drop Path
0x0000
Register Reset Value:
Table 239. DW Overhead Monitor GCC FIFO Access Register
Reset
Value
Bit
Name
Access
Description
15:0
GCC
RO
GCC Data
0x0000
302 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
