VSC6134
Datasheet
3.8.40
DW Section Monitor TTI FIFO Register
Address:
0xF28: Add Path
0x728: Drop Path
0x0000
Register Reset Value:
Table 241. DW Section Monitor TTI FIFO Register
Reset
Value
Bit
Name
Access
Description
15:0
SM_TTI
RO
This register provides access to a 32-word deep, 16-bit
wide FIFO that holds the monitored SM TTI values. The
FIFO has one configurable pointer for both read and write
operations shown in Table 242, page 304. Each time a read
or write operation occurs at this address (0xF29 add or
0x729 drop), the pointer is automatically incremented by 1.
Each of the 32 registers in the FIFO contains two 8-bit
values for TTI. Received TTI values are entered into the
FIFO on a rotating basis. The value of bits 7:0 of address
00000 of the FIFO represents the TTI 0 and the value at
bits 15:8 of address 11111 represents TTI 64. The 64-byte
TTI signal is aligned with the OTU multiframe (MFAS). Byte
0 of the 64-byte TTI signal is present at OTU multiframe
position 00.
0x0000
3.8.41
DW Section Monitor Configuration Register
Address:
0xF29: Add Path
0x729: Drop Path
0x0000
Register Reset Value:
Table 242. DW Section Monitor Configuration Register
Reset
Value
Bit
Name
Access
RO
Description
15:13
12:8
Reserved
SM_TTIPNT
000
R/W
SM TTI MPU read pointer.
00000
This is the MPU read pointer into the SM TTI FIFO that
auto-increments on an MPU read or write.
7
SM_TTIINVD
R/W
SM TTI invalidate.
0
A zero to one transition clears the three SM TTI live bits,
invalidating all SM TTI fields.
6
5
Reserved
RO
0
0
SM_BIAEAUTO
R/W
SM auto BIAE.
A 1 allows SM IAE to set SM BEI to the BIAE condition on
the transmit direction. A ‘0’ disables this function.
4
SM_BIAEMANU
Reserved
R/W
RO
SM manual BIAE.
A 1 forces SM BEI to the BIAE condition on the transmit
direction.
0
3:0
0x0
304 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
