VSC6134
Datasheet
3.8.36
DW Overhead Monitor FTFL FIFO Access Register
Address:
0xF23: Add Path
0x723: Drop Path
0x0000
Register Reset Value:
Table 237. DW Overhead Monitor FTFL FIFO Access Register
Reset
Value
Bit
Name
Access
Description
15:0
FTFL
RO
This register provides access to a 128-word deep, 16-bit
wide FIFO that holds the monitored FTFL values. The FIFO
has one configurable pointer for both read and write
operations shown in Table 236. Each time a read or write
operation occurs at this address (0xF23 Add / 0x723 Drop),
the pointer is automatically incremented by 1. Each of the
128 registers in the FIFO contains two 8-bit values for
FTFL. Received FTFL values are entered into the FIFO on
a rotating basis. The value of bits [7:0] of address 0000000
of the FIFO represents FTFL 0 and the value at bits [15:8]
of address 1111111 of the FIFO represents FTFL 255. The
256-byte FTFL signal is aligned with the OTU multiframe
(MFAS). Byte 0 of the 256-byte FTFL signal is present at
OTU multiframe position 00.
0x0000
301 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
