VSC6134
Datasheet
3.8.22
Standard FEC Opposite Surround Bit Error Count (MSW)
Address:
0xF13: Add Path
0x713: Drop Path
0x0000
Register Reset Value:
Table 223. Standard FEC Opposite Surround Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
SRND_OPP_ERR_UPR
RO
Count of Reed Solomon decoder bit errors with opposite
surroundings of ones or zeros (upper 16 bits of 32 bit
count). “Performance Monitoring,’ page 119
0x0000
3.8.23
Standard FEC Same Surround Bit Error Count (LSW)
Address:
0xF14: Add Path
0x714: Drop Path
0x0000
Register Reset Value:
Table 224. Standard FEC Same Surround Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
SRND_SAME_ERR_LWR
RO
Count of Reed Solomon decoder bit errors with same
surroundings of ones or zeros (lower 16 bits of 32 bit
count). “Performance Monitoring,’ page 119
0x0000
3.8.24
Standard FEC Same Surround Bit Error Count (MSW)
Address:
0xF15: Add Path
0x715: Drop Path
0x0000
Register Reset Value:
Table 225. Standard FEC Same Surround Bit Error Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
SRND_SAME_ERR_UPR
RO
Count of Reed Solomon decoder bit errors with same
surroundings of ones or zeros (upper 16 bits of 32 bit
count). “Performance Monitoring,’ page 119
0x0000
296 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
