VSC6134
Datasheet
3.8.17
DW Overhead Configuration Register 0
Address:
0xF0E: Add Path
0x70E: Drop Path
0xF600
Register Reset Value:
Table 218. DW Overhead Configuration Register 0
Reset
Value
Bit
Name
Access
Description
15:8
LOMTHRSHLD
R/W
Loss-of-multiframe alignment (LOM) threshold.
The default of F6 allows for 3 ms to expire while in the
out-of-multiframe alignment condition before setting the
LOM status bit.
0xF6
7
GAIS_CFG
Reserved.
R/W
RO
Generic AIS configuration.
0
1: Allows Generic AIS detection across the payload stuff
bytes. 0: Excludes the stuff bytes when detecting Generic
AIS.
6:0
0x00
3.8.18
DW Overhead Configuration Register 1
Address:
0xF0F: Add Path
0x70F: Drop Path
0x6000
Register Reset Value:
Table 219. DW Overhead Configuration Register 1
Reset
Value
Bit
Name
Access
Description
15:13
APSPCC_MAT
R/W
APS/PCC match.
011
These bits determine the consecutive number of matching
APS/PCC before setting the APS/PCC live bit active,
indicating valid APS/PCC bytes. The bits also determine,
when the live bit is active, the consecutive number of
mismatching APS/PCC before clearing the APS/PCC live
bit. 0 through 7 values correspond to 1 through 8 matches.
12:0
Reserved
RO
0x000
294 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
