VSC6134
Datasheet
3.8.19
Standard FEC Uncorrectable Code Word Count (LSW)
Address:
0xF10: Add Path
0x710: Drop Path
0x0000
Register Reset Value:
Table 220. Standard FEC Uncorrectable Code Word Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
TOTAL_StFEC_UCW_LWR
RO
Count of total number of Reed Solomon decoder
0x0000
uncorrected code words (lower 16 bits of 32 bit count)
3.8.20
Standard FEC Uncorrectable Code Word Count (MSW)
Address:
0xF11: Add Path
0x711: Drop Path
0x0000
Register Reset Value:
Table 221. Standard FEC Uncorrectable Code Word Count (MSW)
Reset
Value
Bit
Name
Access
Description
15:0
TOTAL_StFEC_UCW_UPR
RO
Count of total number of Reed Solomon decoder
0x0000
uncorrected code words (upper 16 bits of 32 bit count)
3.8.21
Standard FEC Opposite Surround Bit Error Count (LSW)
Address:
0xF12: Add Path
0x712: Drop Path
0x0000
Register Reset Value:
Table 222. Standard FEC Opposite Surround Bit Error Count (LSW)
Reset
Value
Bit
Name
Access
Description
15:0
SRND_OPP_ERR_LWR
RO
Count of Reed Solomon decoder bit errors with opposite
surroundings of ones or zeros (lower 16 bits of 32 bit
count). “Performance Monitoring,’ page 119
0x0000
295 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
