TS7001
With the ADSP-21xx’s TFS and RFS pins of its
SPORT connected together, the TFS is configured
as an output and RFS configured as an input. The
frame synchronization signal generated on the TFS
output serves as the TS7001’s CS input. In this
example, however, since a timer interrupt is used to
control the sampling rate of the ADC, it may not be
possible to perform equidistant sampling (a required
criterion in all signal processing applications) under
certain application conditions.
Figure 17: Interfacing the TS7001 to DSP56xxx-type
DSPs.
The ADSP-21xx’s timer registers are configured in
such a manner that an interrupt is generated
internally at the required sample interval. When the
timer interrupt is received, an ADC control word is
transmitted at the DT output with TFS. The TFS
signal is then used to control the RFS and hence the
data read from the TS7001. When the instruction to
transmit with TFS is executed (that is, AX0 = TX0),
the state of the SCLK is checked. The DSP waits
until the SCLK has toggled high-to-low-to-high
before a transmission will commence. If the timer
and SCLK values are set such that the instruction to
transmit occurs on or near the low-to-high SCLK
transition, data may be transmitted or the DSP may
wait to transmit data until the next clock edge.
A TS7001 to 68HC11 Microcontroller Interface
Connecting the TS7001 to Freescale’s 68HC11 (nee
Motorola’s MC68HC11) is shown in Figure 18. The
microcontroller’s serial peripheral interface (SPI) is
configured for Master Mode (MSTR = 1) with its
Clock Polarity Bit (CPOL) set to 1 and Clock Phase
Bit (CPHA) set to 1. Serial data transfer from the
TS7001 to the 68HC11 requires two 8-bit transfers
and the 68HC11’s SPI is configured by writing to the
SPI Control Register (SPCR) — consult the 68HC11
User Manual for more information.
For example, consider an ADSP-2111 that has been
chosen as the host processor. Since it has a
16-MHz master clock frequency, a SCLKDIV value
of 3 is necessary to program its SPORT serial clock
output to operate at 2MHz for the TS7001
(16MHz ÷ 23 = 2MHz); thus, eight master clock
periods will elapse for every one TS7001 SCLK
period. If the ADSP-2111’s timer registers are
loaded with a value of 803, 100.5 SCLKs will occur
between interrupts and subsequently between
transmit instructions. Because the transmit
instruction occurs on an SCLK edge, non-equidistant
sampling is the result. The DSP will implement
equidistant sampling only if the number of SCLKs
between interrupts is a whole integer number.
Figure 18: Interfacing the TS7001 to 68HC11-type
Microcontrollers.
A TS7001 to 8051 Microcontroller Interface
Using the parallel port of legacy 8051-type (or
equivalent) microcontrollers, a serial interface to the
TS7001 can be designed as shown in Figure 19. As
a
result, full duplex serial transfer to be
A TS7001 to DSP56xxx DSP Interface
Connecting the TS7001 for use with Freescale’s
(nee Motorola’s) DSP56xxx family of DSPs is shown
in Figure 17 where an inverter is used between the
DSP56xxx’s SCꢀ output and the TS7001’s SCLꢀ
input. The DSP56xxx’s SSI (synchronous serial
interface) is configured in synchronous mode (SYN
bit = 1 in CRB) with an internally generated 1-bit
clock period frame sync for both Tx and Rx (Bits
FSL1 = 1 and FSL0 = 0 in CRB). Word length is set
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.
Figure 19: Interfacing the TS7001 to Legacy 8051-type
Microcontrollers.
implemented. The technique involves “bit-banging”
one of the the microcontroller’s I/O ports (for
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RTFDS
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