TS7001
Figure 13: TS7001’s Power Management Mode 4 Operation Diagram.
sampled on the second low-to-high SCLK transition
high-to-low CS transition. In modes where the high-
following the high-to-low CS transition. At the end of
conversion (after the last low-to-high SCLK
transition), the ADC is powered down automatically
back into its standby mode.
to-low CS transition powers up the ADC, the
acquisition time must include a 5-μs power-up delay.
The ADC’s internal track-and-hold moves from track
mode to hold mode on the second low-to-high SCLK
transition and a conversion is also initiated on this
transition. The conversion process takes an
additional 14.5 SCLK cycles to complete. After the
conversion is completed, a subsequent low-to-high
The TS7001’s Serial Interface Description
Figure 14 shows the detailed timing diagram for
TS7001’s serial interface. The serial clock provides
the conversion clock and also controls the transfer of
data to/from the TS7001 during conversion.
CS transition sets the serial data bus back into a
high-Z (or three-state) condition. A new conversion
can be initiated if the CS signal is left low.
The CS signal initiates the serial data transfer and
controls the TS7001’s conversion process. In PM
In dual-channel operation, the current conversion
result is associated to the selected analog channel
programmed during the previous write cycle to the
control register. Therefore, in dual-channel
operation, the system code design must perform a
channel address write for the next conversion while
the current conversion is in progress.
Modes 1, 3, and 4, a high-to-low CS transition
powers up the ADC. In all cases, the CS signal
gates SCLK to the TS7001 and sets the ADC’s
internal track-and-hold into track mode. The analog
input signal is then sampled on the second low-to-
high SCLK transition following the high-to-low CS
transition. Thus, the analog input signal is acquired
during the first 1.5 SCLK clock cycles (tACQ) after the
Writing serial data to the Control Register always
takes place and occurs on the first eight low-to-high
Figure 14: TS7001’s Detailed Serial Interface Timing Diagram.
Page 16
TS7001DS r1p0
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
