TS7001
the supplies by the ADC is commensurately reduced
the longer the TS7001 remains in a powered-down
state.
and PM0 bits of the Control Register. Also
mentioned previously, the TS7001 can be
configured as a read-only ADC by forcing an all
zeros (“0”s) condition in the control register. This can
be easily done by applying a logic LOW at all times
to the DIN pin or hard-wiring the DIN pin directly to
GND.
For example, consider the following TS7001
application configuration: (a) the ADC is powered
from VDD = 3V and is configured for PM Mode 3
(that is, [PM1, PM0] = [1,0], where the ADC’s
internal reference is enabled and the ADC
automatically powers down after the conversion is
completed); and (b) the ADC operates at a
throughput rate of 10 ksps with a 3-MHz SCLK.
Power Management Mode 1 Operation:
[PM1,PM0] = [0,0]
Power Management Operating Mode 1 is used to
control the TS7001’s power-down using the CS pin.
Whenever the CS pin is low, the TS7001 is fully
powered up; whenever the CS pin is high, the
Given the above configuration, the TS7001’s power
consumption during normal operation is 2.1mW at
VDD = 3 V (0.7mA x 3V). Since its power-up delay
time is 5μs and its conversion-plus-acquisition time
is ~5.2μs (tCONVERT + tACQ = 14.5 x tSCLK + 1.5 x tSCLK
= 15.5 x tSCLK), the TS7001 consumes 3.5mW for
10.2μs during each conversion cycle. Since the
conversion cycle time (100μs) is the reciprocal of the
ADC’s throughput rate (10ksps), the average power
consumed by the TS7001 during each conversion
cycle is (10.2/100) × (2.1mW), or 214.2μW. The
TS7001’s power consumption vs. throughput rate
when configured for automatic shutdown post
conversion and operating on a 3V supply is
illustrated in Figure 8.
TS7001 is completely powered down. When the CS
pin is toggled high-to-low, all internal circuitry starts
to power up where it can take as long as 5μs for the
TS7001’s internal circuitry to power up completely.
As a result, any conversion start sequence should
not be initiated during this initial 5μs power-up delay.
Figure 9 shows a general operating diagram of the
TS7001 in PM Mode 1. The analog input signal is
sampled on the second low-to-high SCLK transition
following the initial high-to-low CS transition. System
timing design should incorporate a 5-μs delay
between the high-to-low CS transition and the
Power Management Operating Modes
second
low-to-high
SCLK
transition.
In
microcontroller applications, this is achieved by
Designed to provide flexible power consumption
profiles, the TS7001 incorporates four different
operating modes to optimize the ADC’s power
consumption/throughput-rate ratio. As previously
described in Table 6, the four different modes of
operation in the TS7001 are controlled by the PM1
Figure 9: TS7001’s Power Management Mode 1 Operation Diagram.
TS7001DS r1p0
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RTFDS
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