TS7001
SCLK transitions. However, the TS7001 can be
configured as a read-only device by physically
loading all “zeros” (“0”s) into the Control Register
every time, by applying a logic LOW to the DIN pin
at all times, or by hard-wiring the DIN pin to GND.
When the TS7001 is configured in WRITE/READ
modes, system code design must be designed
always to load the correct data onto the DIN line
when reading data from the TS7001.
Figure 15: Interfacing the TS7001 to TSM320C5x-type
Sixteen serial clock cycles are required to perform
the conversion process and to transfer data
to/access data from the TS7001. In applications
where the first serial clock transition following a high-
DSPs.
and FSX (frame sync transmit) programmed as the
TS7001’s CS input. The TMS320C5x’s serial port
control register (SPC) must be configured in the
following manner:
to-low CS transition is a high-to-low SCLK transition,
DOUT transitions from a high-Z state to a first
leading zero; thus, the first low-to-high SCLK
transition generates the first leading zero on DOUT.
In applications where the first serial clock transition
Table 3: TMS320C5x Serial Port Control Register
Setup
FO
FSM
MCM
TXM
following a high-to-low CS transition is a low-to-high
SCLK transition, the first leading zero may not be set
up in time for the host processor to read it correctly.
However, subsequent DOUT bits are transferred out
on high-to-low SCLK transitions so that they are
ready for the host processor on the following low-to-
high SCLK transition. Thus, the second leading zero
is transferred out on the high-to-low SCLK transition
subsequent to the first low-to-high SCLK transition.
Therefore, DOUT’s final bit in the data transfer is
valid on the 16th low-to-high SCLK transition, having
been transferred out of the ADC on the previous
high-to-low SCLK transition.
0
1
1
1
A TS7001 to ADSP-21xx DSP Interface
The TS7001 is easily interfaced to the ADSP-21xx
(or equivalent) family of DSPs using an inverter
between the ADSP-21xx’s serial clock and the
TS7001 as shown in Figure 16. The ADSP-21xx’s
SPORT control register should be configured in
Alternate Framing mode as shown in Table 4 and
the ADSP-21xx’s serial clock frequency is set in its
SCLKDIV register.
Interfacing the TS7001 to Industry-Standard
Microprocessors and DSPs
The serial interface on the TS7001 allows the ADC
to be directly connected to a number of many
microprocessors and DSPs. How to interface the
TS7001 with some of the more common
microcontroller and DSP serial interface protocols is
covered in this section.
Figure 16: Interfacing the TS7001 to ADSP-21xx-type
DSPs.
A TS7001 to TMS320C5x DSP Interface
Table 4: SPORT0 Control Register Setup
With peripheral serial devices like the TS7001, the
TMS320C5x’s serial interface has a continuous
serial clock and frame synchronization signals to
time the data transfer operations. A single logic
inverter is the only glue logic required between the
TMS320C5x’s CLꢀX output and the TS7001 SCLK
input and is illustrated in the connection diagram of
Figure 15. The TMS320C5x’s serial port is
configured to operate in burst mode using the
TMS320C5x’s internal CLꢀX (serial clock transmit)
Bit(s)
TFSW, RFSW
INVRFS, INVTFS
DTYPE
Setting
1
Description
Alternative framing
Active-low frame signal
Right justified data
16-bit data word
1
00
SLEN
1111
1111
ISCLK
Internal serial clock
Frame every word
TFSR, RFSR
IRFS
1
0
1
ITFS
TS7001DS r1p0
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