TS7001
and performance will degrade. Figure 6 illustrates
how the TS7001’s harmonic performance as a
function of frequency is affected by different source
impedances.
up the TS7001 again. When the TS7001 is
programmed in PM Mode 1 (i.e., [PM1,PM0] = [0,0],
the default condition), the TS7001 is powered down
on a low-to-high CS transition and powers up from
shutdown on a high-to-low CS transition. If the
The TS7001’s Internal 2.5-V Reference
CS pin is toggled low-to-high during the conversion
in this operating mode, the ADC is immediately
powered down.
Using the REF bit (the DB5 bit) in the TS7001’s
Control Register, the TS7001’s internal 2.5-V
reference can be enabled (DB5 cleared to “0”) or
disabled (DB5 set to “1”). If enabled (the default
condition), the internal voltage reference can be
used in applications for other purposes and, if this is
desired, the reference should be buffered by an
external, precision op amp. If an external, precision
voltage reference is used instead of the TS7001’s
internal reference, the internal reference is
automatically overdriven. In this case, the TS7001’s
internal reference should be disabled by setting the
REF bit in the control register. When the internal
reference is disabled, switch SW1 as shown in
Figure 7 opens and the input impedance seen at the
AIN1/VREF pin is the reference buffer’s input
Cold-Start and Standby Power-Up Delay Times
When VDD is first applied to the TS7001 (in other
words, from cold start-up), the ADC powers up in PM
Mode 1 ([PM1,PM0] = [0,0]). Upon a subsequent
high-to-low CS transition, the TS7001’s power-up
delay time is approximately 5μs. When using an
external voltage reference in single-channel
operation or when the TS7001 is powered up from
standby mode (PM Mode 4), its power-up delay time
is approximately 1μs because the internal reference
has been either disabled (refer to Control Register
DB5) or the internal reference has remained
powered up (via PM Mode 4). Since the TS7001’s
power-up delay time PM Mode 4 is very short,
powering up the ADC and executing a conversion
with valid results in the same read/write operation is
feasible.
TS7001 Power Consumption vs. Throughput
Rate Considerations
Figure 7: TS7001’s Integrated 2.5-V VREF Circuitry.
In operating the TS7001 in auto-shutdown mode
(PM Mode 3), in auto-standby mode (PM Mode 4),
or in PM Mode 1, the average power drawn by the
TS7001 decreases at lower throughput rates. As
shown in Figure 8, the average power drawn from
impedance, approximately in the gigaohm range
(GΩ). When the internal reference is enabled, the
input impedance at the AIN1/VREF pin is typically
10kΩ. When the TS7001 is configured for two-
channel operation, the TS7001’s reference is set
internally to VDD.
Figure 8: TS7001 Power Consumption
vs Throughput Rate
10
1
TS7001’s Power-Down Operating Modes
The TS7001 provides flexible power management to
allow the user to achieve the best power
performance for a given throughput rate. The four
power management options are selected by
programming the TS7001’s power management bits
(“PM” Bits PM1 and PM0) in the control register as
summarized in Table 6. When the PM bits are
programmed for either of the auto power-down
modes (PM Mode 3 or 4), the TS7001 is powered-
down on the 16th low-to-high SCLK transition after a
VDD = 3V
SCLK = 3MHz
0.1
0.01
high-to-low CS transition. The first high-to-low SCLK
transition after a high-to-low CS transition powers-
0
60 80 100 120 140 160180
20 40
THROUGHPUT RATE - ksps
Page 12
TS7001DS r1p0
RTFDS
TOUCHSTONE [ TOUCHSTONE SEMICONDUCTOR INC ]
