TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-83. IOUTE1 Register (continued)
R-0h
R/W-X
表 7-85. IOUTE1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTE1
R
0h
Reserved
R/W
X
Output current setting for OUTE1
Load EEPROM register data when reset
7.6.2.11 IOUTF0 Register (Offset = 5Ah) [Reset = X]
IOUTF0 is shown in 图 7-84 and described in 表 7-86.
Return to the Summary Table.
图 7-84. IOUTF0 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTF0
R/W-X
表 7-86. IOUTF0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTF0
R
0h
Reserved
R/W
X
Output current setting for OUTF0
Load EEPROM register data when reset
7.6.2.12 IOUTF1 Register (Offset = 5Bh) [Reset = X]
IOUTF1 is shown in 图 7-85 and described in 表 7-87.
Return to the Summary Table.
图 7-85. IOUTF1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTF1
R/W-X
表 7-87. IOUTF1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTF1
R
0h
Reserved
R/W
X
Output current setting for OUTF1
Load EEPROM register data when reset
7.6.2.13 IOUTG0 Register (Offset = 5Ch) [Reset = X]
IOUTG0 is shown in 图 7-86 and described in 表 7-88.
Return to the Summary Table.
图 7-86. IOUTG0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTG0
R/W-X
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
82
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