TPS929160-Q1
ZHCSNG0 – APRIL 2023
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7.6.2 IOUT Registers
表 7-74 lists the memory-mapped registers for the IOUT registers. All register offset addresses not listed in 表
7-74 should be considered as reserved locations and the register contents should not be modified.
Output Current Setting
表 7-74. IOUT Registers
Offset
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
Acronym
IOUTA0
IOUTA1
IOUTB0
IOUTB1
IOUTC0
IOUTC1
IOUTD0
IOUTD1
IOUTE0
IOUTE1
IOUTF0
IOUTF1
IOUTG0
IOUTG1
IOUTH0
IOUTH1
IOUTAR
IOUTBR
IOUTCR
IOUTDR
IOUTER
IOUTFR
IOUTGR
IOUTHR
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Output Current Setting for OUTA0
Output Current Setting for OUTA1
Output Current Setting for OUTB0
Output Current Setting for OUTB1
Output Current Setting for OUTC0
Output Current Setting for OUTC1
Output Current Setting for OUTD0
Output Current Setting for OUTD1
Output Current Setting for OUTE0
Output Current Setting for OUTE1
Output Current Setting for OUTF0
Output Current Setting for OUTF1
Output Current Setting for OUTG0
Output Current Setting for OUTG1
Output Current Setting for OUTH0
Output Current Setting for OUTH1
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Complex bit access types are encoded to fit into small table cells. 表 7-75 shows the codes that are used for
access types in this section.
表 7-75. IOUT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.2.1 IOUTA0 Register (Offset = 50h) [Reset = X]
IOUTA0 is shown in 图 7-74 and described in 表 7-76.
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English Data Sheet: SLVSG60
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