TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-77. IOUTB1 Register
7
6
5
4
3
2
1
1
1
1
0
RESERVED
R-0h
IOUTB1
R/W-X
表 7-79. IOUTB1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTB1
R
0h
Reserved
R/W
X
Output current setting for OUTB1
Load EEPROM register data when reset
7.6.2.5 IOUTC0 Register (Offset = 54h) [Reset = X]
IOUTC0 is shown in 图 7-78 and described in 表 7-80.
Return to the Summary Table.
图 7-78. IOUTC0 Register
7
6
5
4
3
2
0
0
0
RESERVED
R-0h
IOUTC0
R/W-X
表 7-80. IOUTC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTC0
R
0h
Reserved
R/W
X
Output current setting for OUTC0
Load EEPROM register data when reset
7.6.2.6 IOUTC1 Register (Offset = 55h) [Reset = X]
IOUTC1 is shown in 图 7-79 and described in 表 7-81.
Return to the Summary Table.
图 7-79. IOUTC1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTC1
R/W-X
表 7-81. IOUTC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTC1
R
0h
Reserved
R/W
X
Output current setting for OUTC1
Load EEPROM register data when reset
7.6.2.7 IOUTD0 Register (Offset = 56h) [Reset = X]
IOUTD0 is shown in 图 7-80 and described in 表 7-82.
Return to the Summary Table.
图 7-80. IOUTD0 Register
7
6
5
4
3
2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
80
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