TPS929160-Q1
ZHCSNG0 – APRIL 2023
www.ti.com.cn
图 7-80. IOUTD0 Register (continued)
RESERVED
IOUTD0
R-0h
R/W-X
表 7-82. IOUTD0 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTD0
R
0h
Reserved
R/W
X
Output current setting for OUTD0
Load EEPROM register data when reset
7.6.2.8 IOUTD1 Register (Offset = 57h) [Reset = X]
IOUTD1 is shown in 图 7-81 and described in 表 7-83.
Return to the Summary Table.
图 7-81. IOUTD1 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTD1
R/W-X
表 7-83. IOUTD1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTD1
R
0h
Reserved
R/W
X
Output current setting for OUTD1
Load EEPROM register data when reset
7.6.2.9 IOUTE0 Register (Offset = 58h) [Reset = X]
IOUTE0 is shown in 图 7-82 and described in 表 7-84.
Return to the Summary Table.
图 7-82. IOUTE0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTE0
R/W-X
表 7-84. IOUTE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTE0
R
0h
Reserved
R/W
X
Output current setting for OUTE0
Load EEPROM register data when reset
7.6.2.10 IOUTE1 Register (Offset = 59h) [Reset = X]
IOUTE1 is shown in 图 7-83 and described in 表 7-85.
Return to the Summary Table.
图 7-83. IOUTE1 Register
7
6
5
4
3
2
RESERVED
IOUTE1
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
TI [ TEXAS INSTRUMENTS ]
