TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-128. CTRLGATE Register (continued)
表 7-134. CTRLGATE Register Field Descriptions
Bit
Field
CTRLGATE
Type
Reset
Description
7-0
R/W
0h
Gate register for DEBUG, LOCK and CLRREG registers access,
write 43h, 4Fh, 44h and 45h one-byte by one-byte
7.6.4.8 EEP Register (Offset = 97h) [Reset = 00h]
EEP is shown in 图 7-129 and described in 表 7-135.
Return to the Summary Table.
图 7-129. EEP Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
EEPPROG
R/W-0h
EEPMODE
R/W-0h
表 7-135. EEP Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
EEPPROG
R
0h
Reserved
R/W
0h
EEPROM burning starts in EEPROM programming state only,
automatically returns to 0
0
EEPMODE
R/W
0h
EEPROM programming state setting
0h = Disabled
1h = Enabled
7.6.4.9 EEPGATE Register (Offset = 98h) [Reset = 00h]
EEPGATE is shown in 图 7-130 and described in 表 7-136.
Return to the Summary Table.
图 7-130. EEPGATE Register
7
6
5
4
3
2
1
0
EEPGATE
R/W-0h
表 7-136. EEPGATE Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPGATE
R/W
0h
Gate register for EEP registers access, write 00h, 04h, 02h, 09h, 02h
and 09h one-byte by one-byte
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English Data Sheet: SLVSG60
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