SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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Contents
1
F280x, F2801x, C280x DSPs
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9
2
3
4
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1.2
Getting Started
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Introduction
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2.1
Pin Assignments
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2.2
Signal Descriptions
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Functional Overview
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3.1
Memory Maps
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3.2
Brief Descriptions
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3.2.1
C28x CPU
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3.2.2
Memory Bus (Harvard Bus Architecture)
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3.2.3
Peripheral Bus
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3.2.4
Real-Time JTAG and Analysis
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3.2.5
Flash
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3.2.6
ROM
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3.2.7
M0, M1 SARAMs
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3.2.8
L0, L1, H0 SARAMs
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3.2.9
Boot ROM
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3.2.10 Security
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3.2.11 Peripheral Interrupt Expansion (PIE) Block
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3.2.12 External Interrupts (XINT1, XINT2, XNMI)
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3.2.13 Oscillator and PLL
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3.2.14 Watchdog
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3.2.15 Peripheral Clocking
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3.2.16 Low-Power Modes
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3.2.17 Peripheral Frames 0, 1, 2 (PFn)
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3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
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3.2.19 32-Bit CPU-Timers (0, 1, 2)
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3.2.20 Control Peripherals
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3.2.21 Serial Port Peripherals
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3.3
Register Map
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3.4
Device Emulation Registers
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3.5
Interrupts
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3.5.1
External Interrupts
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3.6
System Control
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3.6.1
OSC and PLL Block
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3.6.1.1
External Reference Oscillator Clock Option
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3.6.1.2
PLL-Based Clock Module
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3.6.1.3
Loss of Input Clock
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3.6.2
Watchdog Block
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3.7
Low-Power Modes Block
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Peripherals
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4.1
32-Bit CPU-Timers 0/1/2
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4.2
Enhanced PWM Modules (ePWM1/2/3/4/5/6)
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4.3
Hi-Resolution PWM (HRPWM)
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1.1
Features
Contents
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2
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