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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
Digital Signal Processors
Check for
Samples:
1
1.1
1234
F280x, F2801x, C280x DSPs
Features
• 128-Bit Security Key/Lock
– Protects Flash/OTP/L0/L1 Blocks
– Prevents Firmware Reverse Engineering
• Three 32-Bit CPU Timers
• Enhanced Control Peripherals
– Up to 16 PWM Outputs
– Up to 6 HRPWM Outputs With 150-ps MEP
Resolution
– Up to Four Capture Inputs
– Up to Two Quadrature Encoder Interfaces
– Up to Six 32-bit/Six 16-bit Timers
• Serial Port Peripherals
– Up to 4 SPI Modules
– Up to 2 SCI (UART) Modules
– Up to 2 CAN Modules
– One Inter-Integrated-Circuit (I2C) Bus
• 12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Fast Conversion Rate:
80 ns - 12.5 MSPS (F2809 only)
160 ns - 6.25 MSPS (280x)
267 ns - 3.75 MSPS (F2801x)
– Internal or External Reference
• Up to 35 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
• Development Support Includes
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– Digital Motor Control and Digital Power
Software Libraries
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
• High-Performance Static CMOS Technology
– 100 MHz (10-ns Cycle Time)
– 60 MHz (16.67-ns Cycle Time)
– Low-Power (1.8-V Core, 3.3-V I/O) Design
• JTAG Boundary Scan Support
(1)
• High-Performance 32-Bit CPU ( TMS320C28x™)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)
• On-Chip Memory
– F2809: 128K x 16 Flash, 18K x 16 SARAM
F2808: 64K x 16 Flash, 18K x 16 SARAM
F2806: 32K x 16 Flash, 10K x 16 SARAM
F2802: 32K x 16 Flash, 6K x 16 SARAM
F2801: 16K x 16 Flash, 6K x 16 SARAM
F2801x: 16K x 16 Flash, 6K x 16 SARAM
– 1K x 16 OTP ROM (Flash Devices Only)
– C2802: 32K x 16 ROM, 6K x 16 SARAM
C2801: 16K x 16 ROM, 6K x 16 SARAM
• Boot ROM (4K x 16)
– With Software Boot Modes (via SCI, SPI,
CAN, I2C, and Parallel I/O)
– Standard Math Tables
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
• Any GPIO A Pin Can Be Connected to One of
the Three External Core Interrupts
• Peripheral Interrupt Expansion (PIE) Block That
Supports All 43 Peripheral Interrupts
(1)
1
IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
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3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C28x, Code Composer Studio, DSP/BIOS, MicroStar BGA, C28x, TI, TMS320C2000 are trademarks of Texas Instruments.
eZdsp is a trademark of Spectrum Digital.
All other trademarks are the property of their respective owners.
Copyright © 2003–2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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