SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the
TMS320x280x, 2801x, 2804x DSP System Control and
Interrupts Reference Guide
(literature number
3.6
System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes.
shows the various clock and reset domains in the 280x devices that will be
discussed.
Reset
SYSCLKOUT
(A)
Watchdog
Block
XRS
Peripheral Reset
CLKIN
28x
CPU
(A)
X1
PLL
OSC
X2
Peripheral
Registers
System
Control
Registers
CPU
Timers
Clock Enables
Power
Modes
Control
XCLKIN
Peripheral
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
I/O
Peripheral Bus
Peripheral
Registers
Low-Speed Prescaler
eCAN-A/B
I2C-A
I/O
GPIO
MUX
GPIOs
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
I/O
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
A.
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-9. Clock and Reset Domains
46
Functional Overview
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