SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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(2)
Table 3-10. Peripheral Frame 2 Registers
(1)
NAME
System Control Registers
SPI-A Registers
SCI-A Registers
External Interrupt Registers
ADC Registers
SPI-B Registers
SCI-B Registers
SPI-C Registers
SPI-D Registers
I2C Registers
(1)
(2)
ADDRESS RANGE
0x7010 – 0x702F
0x7040 – 0x704F
0x7050 – 0x705F
0x7070 – 0x707F
0x7100 – 0x711F
0x7740 – 0x774F
0x7750 – 0x775F
0x7760 – 0x776F
0x7780 – 0x778F
0x7900 – 0x792F
SIZE (x16)
32
16
16
16
32
16
16
16
16
48
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
Missing segments of memory space are reserved and should not be used in applications.
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in
Table 3-11. Device Emulation Registers
NAME
ADDRESS
RANGE
0x0880
0x0881
0x0882
SIZE (x16)
2
1
Device Configuration Register
Part ID Register
0x002C
(1)
- F2801
0x0024 – F2802
0x0034 – F2806
0x003C – F2808
0x00FE – F2809
0x0014 – F28016
0x001C – F28015
0xFF2C – C2801
0xFF24 – C2802
0x0000 – Silicon Rev.
0x0001 – Silicon Rev.
0x0002 – Silicon Rev.
0x0003 – Silicon Rev.
0 – TMX
A – TMX
B – TMS
C – TMS
DESCRIPTION
DEVICECNF
PARTID
REVID
0x0883
1
Revision ID Register
Revision ID Register
PROTSTART
PROTRANGE
(1)
0x0884
0x0885
1
1
0x0000 – Silicon rev. 0 – TMS (F2809 only)
Block Protection Start Address Register
Block Protection Range Address Register
The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.
3.5
Interrupts
shows how the various interrupt sources are multiplexed within the 280x devices.
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as
shown in
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
42
Functional Overview
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