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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
3
Functional Overview
Memory Bus
TINT0
TINT1
32-bit CPU TIMER 1
TINT2
32-bit CPU TIMER 2
INT14
PIE
(96 Interrupts)
(A)
32-bit CPU TIMER 0
7
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
INT[12:1]
32
4
External Interrupt
Control
SCI-A/B
FIFO
FIFO
FIFO
NMI, INT13
L0 SARAM
4K x 16
(0-wait)
L1 SARAM
4K x 16
(0-wait)
(B)
16
2
SPI-A/B/C/D
I2C-A
4
H0 SARAM
8K x 16
(0-wait)
(C)
eCAN-A/B (32 mbox)
eQEP1/2
eCAP1/2/3/4
(4 32-bit Timers)
ePWM1/2/3/4/5/6
(12 PWM Outputs,
6 Trip Zones,
6 16-bit Timers)
FLASH
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (F2801x)
C28x CPU
(100 MHz)
ROM
32K x 16 (C2802)
16K x 16 (C2801)
GPIO MUX
8
4
12
6
GPIOs
(35)
32
System Control
XCLKOUT
XRS
XCLKIN
X1
X2
SYSCLKOUT
RS
(Oscillator, PLL,
Peripheral Clocking,
Low-Power Modes,
Watchdog)
CLKIN
OTP
1K x 16
(D)
ADCSOCA/B
SOCA/B
12-Bit ADC
16 Channels
Boot ROM
4K x 16
(1-wait state)
Protected by the code-security module.
Peripheral Bus
A.
B.
C.
D.
43 of the possible 96 interrupts are used on the devices.
Not available in F2802, F2801, C2802, and C2801.
Not available in F2806, F2802, F2801, C2802, and C2801.
The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.
Figure 3-1. Functional Block Diagram
Copyright © 2003–2011, Texas Instruments Incorporated
Functional Overview
25
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