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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
3.6.1.2
PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
Table 3-16. PLLCR Register Bit Definitions
PLLCR[DIV]
(1)
0000 (PLL bypass)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011–1111
(1)
(2)
SYSCLKOUT
(CLKIN)
(2)
OSCCLK/n
(OSCCLK*1)/n
(OSCCLK*2)/n
(OSCCLK*3)/n
(OSCCLK*4)/n
(OSCCLK*5)/n
(OSCCLK*6)/n
(OSCCLK*7)/n
(OSCCLK*8)/n
(OSCCLK*9)/n
(OSCCLK*10)/n
Reserved
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.
NOTE
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to
the core. This bit must be 0 before writing to the PLLCR and must only be set after
PLLSTS[PLLLOCKS] = 1.
The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Copyright © 2003–2011, Texas Instruments Incorporated
Functional Overview
49
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