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Advisory
— Memory: Prefetching Beyond Valid Memory
Advisory
Revision(s) Affected
Details
Memory: Prefetching Beyond Valid Memory
0, A
The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the
prefetch occurs past the end of valid memory, then the CPU may receive an invalid
opcode.
The prefetch queue is 8 x16 words in depth. Therefore, code should not come within
8 words of the end of valid memory. This restriction applies to all memory regions and all
memory types (flash, OTP, SARAM, XINTF) on the device. Prefetching across the
boundary between two valid memory blocks is all right.
Example 1: M1 ends at address 0x7FF and is not followed by another memory block.
Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF
should not be used for code.
Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0
can be stored up to and including address 0x3FF. Code can also cross into M1 up to
and including address 0x7F7.
Workaround
Advisory
Revision(s) Affected
Details
Memory: M1 Memory Access Conflict
0
If an opcode fetch is issued to M1 while a write is pending, then an arbitration condition
can cause the write to be lost.
This has been fixed in Rev A silicon.
Workaround(s)
Advisory
Revision(s) Affected
Details
Memory: Possible Incorrect Operation of XINTF Module After Power Up
0, A
The XINTF module may not get reset properly upon power up. When this happens,
accesses to XINTF addresses may cause the CPU to hang. This issue occurs only upon
power up. It does not happen for other resets such as a reset initiated by the watchdog
or an external (warm) reset using the XRS pin.
After coming out of reset, software should force a watchdog (WD) reset if WDFLAG = 0
in the WDCR register. WDFLAG = 0 implies that an external reset occurred, for example,
a power-on reset. After exiting the WD reset, WDFLAG will be 1. In this case, software
should clear the WDFLAG bit before continuing normal code execution. This issue
affects only the XINTF module.
Workaround(s)
SPRZ272F – September 2007 – Revised April 2011
TMS320F2833x and TMS320F2823x DSC Silicon Errata
© 2007–2011, Texas Instruments Incorporated
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