Advisory — SCI: Incorrect Operation of SCI in Address Bit Mode
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Advisory
SCI: Incorrect Operation of SCI in Address Bit Mode
0, A
Revision(s) Affected
Details
SCI does not look for STOP bit after the ADDR bit. Instead, SCI starts looking for the
start bit beginning on sub-sample 6 of the ADDR bit. Slow rise-time from ADDR to STOP
bit can cause the false START bit to occur since the 4th sub-sample for the start bit may
be sensed low.
Expected Operation:
majority
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majority
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start bit is 4
consecutive
zero bits
SCICLK
SCIRXD
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
ADDR bit
STOP bit
START bit
Erroneous Operation:
majority
vote
majority
vote
SCICLK
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
SCIRXD
ADDR bit
STOP bit
START bit
Figure 3. Difference Between Expected and Erroneous Operation of START Bit
Workaround(s)
Program the baud rate of the SCI to be slightly slower than the actual. This will cause
the 4th sub-sample of the false START bit to be delayed in time, and therefore occur
more towards the middle of the STOP bit (away from the signal transition region). The
amount of baud slowing needed depends on the rise-time of the signal in the system.
Alternatively, IDLE mode of the SCI module may be used, if applicable.
10
TMS320F2833x and TMS320F2823x DSC Silicon Errata
SPRZ272F–September 2007–Revised April 2011
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