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Advisory
— ADC: Simultaneous Sampling Latency
Advisory
Revision(s) Affected
Details
ADC: Simultaneous Sampling Latency
0, A
When the ADC conversions are initiated in simultaneous mode, the first sample pair will
not give correct conversion results.
1. If the ADC is used with a sampling window
≤
160 nS, then the first sample pair must
be discarded and a second sample of the same pair must be taken. For instance, if the
sequencer is set to sample channel A0:B0/A1:B1/A2:B2 in that order, then load the
sequencer with A0:B0/A0:B0/A1:B1/A2:B2 and only use the last three conversions.
2. If the ADC is used with a sampling window greater than 160 ns, there is no issue.
Workaround(s)
Advisory
Revision(s) Affected
Details
eCAN: Abort Acknowledge Bit Not Set
0, A
After setting a Transmission Request Reset (TRR) register bit to abort a message, there
are some rare instances where the TRRn and TRSn bits will clear without setting the
Abort Acknowledge (AAn) bit. The transmission itself is correctly aborted, but no interrupt
is asserted and there is no indication of a pending operation.
In order for this rare condition to occur, all of the following conditions must happen:
1. The previous message was not successful, either because of lost arbitration or
because no node on the bus was able to acknowledge it or because an error frame
resulted from the transmission. The previous message need not be from the same
mailbox in which a transmit abort is currently being attempted.
2. The TRRn bit of the mailbox should be set in a CPU cycle immediately following the
cycle in which the TRSn bit was set. The TRSn bit remaining set due to incompletion
of transmission satisfies this condition as well. i.e. the TRSn bit could have been set
in the past, but the transmission remains incomplete.
3. The TRRn bit must be set in the exact SYSCLKOUT cycle where the CAN module is
in idle state for one cycle. The CAN module is said to be in idle state when it is not in
the process of receiving/transmitting data.
If these conditions occur, then the TRRn and TRSn bits for the mailbox will clear t
clr
SYSCLKOUT cycles after the TRR bit is set where:
t
clr
= [(mailbox_number) * 2] + 3 SYSCLKOUT cycles
The TAn and AAn bits will not be set if this condition occurs. Normally, either the TA or
AA bit sets after the TRR bit goes to zero.
Workaround(s)
When this problem occurs, the TRRn and TRSn bits will clear within t
clr
SYSCLKOUT
cycles. To check for this condition, first disable the interrupts. Check the TRRn bit t
clr
SYSCLKOUT cycles after setting the TRRn bit to make sure it is still set. A set TRRn bit
indicates that the problem did not occur.
If the TRRn bit is cleared, it could be because of the normal end of a message and the
corresponding TAn or AAn bit is set. Check both the TAn and AAn bits. If either one of
the bits is set, then the problem did not occur. If they are both zero, then the problem did
occur. Handle the condition like the interrupt service routine would except that the AAn
bit does not need clearing now.
If the TAn or AAn bit is set, then the normal interrupt routine will happen when the
interrupt is re-enabled.
SPRZ272F – September 2007 – Revised April 2011
TMS320F2833x and TMS320F2823x DSC Silicon Errata
© 2007–2011, Texas Instruments Incorporated
11
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