Advisory — GPIO: GPIO Qualification
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Advisory
GPIO: GPIO Qualification
Revision(s) Affected
Details
0, A
If a GPIO pin is configured for "n" SYSCLKOUT cycle qualification period
(where 1 ≤ n ≤ 510) with "m" qualification samples (m = 3 or 6), it is possible that an
input pulse of [n * m – (n – 1)] width may get qualified (instead of n * m). This depends
upon the alignment of the asynchronous GPIO input signal with respect to the phase of
the internal prescaled clock, and hence, is not deterministic. The probability of this kind
of wrong qualification occurring is "1/n".
Worst-case example:
If n = 510, m = 6, a GPIO input width of (n * m) = 3060 SYSCLKOUT cycles is required
to pass qualification. However, because of the issue described in this advisory, the
minimum GPIO input width which may get qualified is [n * m – (n – 1)] = 3060 – 509 =
2551 SYSCLKOUT cycles.
Workaround(s)
None. Ensure a sufficient margin is in the design for input qualification.
Advisory
Boot to XINTF x16, x32 and Parallel Boot Setup Issue
Revision(s) Affected
Details
0
The following signals are not configured for XINTF functionality in the GPIO MUX
registers: XZCS6, XA19, XWE0, XA16.
Workaround
This has been fixed in Rev A silicon.
12
TMS320F2833x and TMS320F2823x DSC Silicon Errata
SPRZ272F–September 2007–Revised April 2011
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