TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 5-3. Available Memory Page Protection Scheme with Privilege ID
PRIVID MODULE
PRIVILEGE MODE
Inherited from CPU(1)
Inherited from CPU(1)
Inherited from CPU(1)
User
DESCRIPTION
C64x+ Megamodule Core 0
C64x+ Megamodule Core 1
C64x+ Megamodule Core 2
EMAC
0
1
2
3
4
5
User
RapidIO and RapidIO CPPI
RAC BE0 and RAC BE1
User
(1) Also applies to EDMA3 transfers that are programmed by the CPU.
Table 5-4. Available Memory Page Protection Scheme with AIDx and Local Bits
AIDx BIT
LOCAL BIT
DESCRIPTION
(x=0,1,2,3,4,5)
0
0
0
1
No access to memory page is permitted.
Only direct access by CPU is permitted
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA
accesses initiated by the CPU)
1
1
0
1
All accesses permitted
Faults are handled by software in an interrupt (or exception, programmable within each C64x+
Megamodule interrupt controller) service routine. A CPU or DMA access to a page without the proper
permissions will:
•
•
•
Block the access - reads return zero, writes are voided.
Capture the initiator in a status register - ID, address, and access type are stored.
Signal event to CPU interrupt controller.
The software is responsible for taking corrective action to respond to the event and resetting the error
status in the memory controller.
5.4 Bandwidth Management
When multiple requesters contend for a single C64x+ Megamodule resource, the conflict is solved by
granting access to the highest priority requestor. The following four resources are managed by the
Bandwidth Management control hardware:
•
•
•
•
Level 1 Program (L1P) SRAM/Cache
Level 1 Data (L1D) SRAM/Cache
Level 2 (L2) SRAM/Cache
Memory-mapped registers configuration bus
The priority level for operations initiated within the C64x+ Megamodule; e.g., CPU-initiated transfers,
user-programmed cache coherency operations, and IDMA-initiated transfers, are declared through
registers in the C64x+ Megamodule. The priority level for operations initiated outside the C64x+
Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see
Section 4.4. System peripherals with no fields in PRI_ALLOC have their own registers to program their
priorities.
5.5 Power-Down Control
The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The
power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache
control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used
to design systems for lower overall system power requirements. Note that the device does not support
power-down modes for the L2 memory at this time.
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C64x+ Megamodule
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