TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 5-6. Megamodule Interrupt Registers (continued)
HEX ADDRESS
ACRONYM
-
REGISTER NAME
0180 0030 - 0180 003C
0180 0040
Reserved
EVTCLR0
EVTCLR1
EVTCLR2
EVTCLR3
-
Event Clear Register 0 (Events [31:0])
Event Clear Register 1
0180 0044
0180 0048
Event Clear Register 2
0180 004C
Event Clear Register 3
0180 0050 - 0180 007C
0180 0080
Reserved
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
-
Event Mask Register 0 (Events [31:0])
Event Mask Register 1
0180 0084
0180 0088
Event Mask Register 2
0180 008C
Event Mask Register 3
0180 0090 - 0180 009C
0180 00A0
Reserved
MEVFLAG0
MEVFLAG1
MEVFLAG2
MEVFLAG3
-
Masked Event Flag Status Register 0 (Events [31:0])
Masked Event Flag Status Register 1
Masked Event Flag Status Register 2
Masked Event Flag Status Register 3
Reserved
0180 00A4
0180 00A8
0180 00AC
0180 00B0 - 0180 00BC
0180 00C0
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
-
Exception Mask Register 0 (Events [31:0])
Exception Mask Register 1
Exception Mask Register 2
Exception Mask Register 3
Reserved
0180 00C4
0180 00C8
0180 00CC
0180 00D0 - 0180 00DC
0180 00E0
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
-
Masked Exception Flag Register 0(Events [31:0])
Masked Exception Flag Register 1
Masked Exception Flag Register 2
Masked Exception Flag Register 3
Reserved
0180 00E4
0180 00E8
0180 00EC
0180 00F0 - 0180 00FC
0180 0100
-
Reserved
0180 0104
INTMUX1
INTMUX2
INTMUX3
-
Interrupt Multiplexer Register 1
Interrupt Multiplexer Register 2
Interrupt Multiplexer Register 3
Reserved
0180 0108
0180 010C
0180 0110 - 0180 013C
0180 0140
AEGMUX0
AEGMUX1
-
Advanced Event Generator Mux Register 0
Advanced Event Generator Mux Register 1
Reserved
0180 0144
0180 0148 - 0180 017C
0180 0180
INTXSTAT
INTXCLER
INTDMASK
-
Interrupt Exception Status Register
Interrupt Exception Clear Register
Dropped Interrupt Mask Register
Reserved
0180 0184
0180 0188
0180 0188 - 0180 01BC
0180 01C0
EVTASRT
-
Event Asserting Register (boot complete register)(1)
0180 01C4 - 0180 FFFF
Reserved
(1) Only bit 4 is used, all other bits are reserved. Bit 4 is write only and has the default 0. After boot is complete, bit 4 is set to 1 and Cores
1 and 2 are released out of reset and start executing their codes.
Table 5-7. Megamodule Power-Down Control Registers
HEX ADDRESS
0181 0000
ACRONYM
PDCCMD
-
REGISTER NAME
Power-Down Controller Command Register
Reserved
0181 0004 - 0181 1FFF
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C64x+ Megamodule
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