TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
3.5 Inter-DSP Interrupt Registers (IPCGR0-IPCGR2 and IPCAR0-IPCAR2)
The IPCGRn (IPCGR0 thru IPCGR2) and IPCARn (IPCAR0 thru IPCAR2) registers facilitate inter-DSP
interrupts. This can be utilized by external hosts or C64x+ megamodules to generate interrupts to other
DSPs. A write of 1 to the IPCG field of IPCGRn register generates an interrupt pulse to C64x+
Megamodulen (n = 0-2). These registers also provide a source ID, by which up to 28 different sources of
interrupts can be identified.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 SRCS22 SRCS21 SRCS20 SRCS19 SRCS18 SRCS17 SRCS16 SRCS15 SRCS14 SRCS13 SRCS12
R/W-0
15
R/W-0
14
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
3
R/W-0
R/W-0
1
R/W-0
13
12
11
10
9
8
7
6
5
4
0
SRCS11 SRCS10
R/W-0 R/W-0
SRCS9
R/W-0
SRCS8
R/W-0
SRCS7
R/W-0
SRCS6
R/W-0
SRCS5
R/W-0
SRCS4
R/W-0
SRCS3
R/W-0
SRCS2
R/W-0
SRCS1
R/W-0
SRCS0
R/W-0
Reserved
R-000
IPCG
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-2. IPC Generation Registers (IPCGR0-IPCGR2)
Table 3-5. IPC Generation Registers (IPCGR0-IPCGR2) Field Descriptions
Bit
Field
Value Description
31:4
SRCS[27:0]
Write:
0
1
No effect
Set register bit
Read:
Returns current value of internal register bit
3:1
0
Reserved
IPCG
Reserved
Write:
0
1
No effect
Create an inter-DSP interrupt pulse to the corresponding C64x+ megamodule (C64x+
Megamodule0 for IPCGR0, etc.)
Read:
Returns 0, no effect
50
Device Configuration
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