TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
If one of the above modules is used in the selected boot mode, the ROM code will automatically enable
the used module.
All other modules come up enabled by default and there is no special software sequence to enable.
For more detailed information on the PSC usage, see the TMS320TCI6487/8 DSP Power/Sleep Controller
(PSC) User's Guide (literature number SPRUEF3).
3.3 Device State Control Registers
The TCI6487/8 device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 3-2.
Table 3-2. Device State Control Registers
ADDRESS START
ADDRESS END
SIZE
ACRONYM
DESCRIPTION
0288 0800
0288 0803
4B
DEVCFG1
The first register with the parameters is set through
software to configure different components on the device
0288 0804
0288 0807
4B
DEVSTAT
Stores all parameters latched from configuration pins or
configured through the DEVCFG register
0288 0808
0288 080C
0288 0810
0288 0814
0288 080B
0288 080F
0288 0813
0288 0817
4B
4B
4B
4B
DSP_BOOT_ADDR0
DSP_BOOT_ADDR1
DSP_BOOT_ADDR2
DEVID
The boot address for C64x+ Megamodule Core 0
The boot address for C64x+ Megamodule Core 1
The boot address for C64x+ Megamodule Core 2
Parameters for DSP device IDs also referred to as JTAG
or BSDL IDs. These must be readable by the
configuration bus so that this can be accessed via JTAG
and CPU
0288 0818
0288 0828
0288 082C
0288 0830
0288 0834
0288 0840
0288 0900
0288 0827
0288 082B
0288 082F
0288 0833
0288 083B
0288 08FF
0288 0903
16B
4B
Reserved
Reserved
Reserved
Reserved
EFUSE_MAC
Reserved
IPCGR0
4B
4B
8B
Required for EMAC boot
N/A
192B
4B
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 0904
0288 0908
0288 0907
0288 090B
4B
4B
IPCGR1
IPCGR2
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 090C
0288 0940
0288 093F
0288 0943
52B
4B
Reserved
IPCAR0
N/A
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 0944
0288 0948
0288 0947
0288 094B
4B
4B
IPCAR1
IPCAR2
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Submit Documentation Feedback
Device Configuration
47
TI [ TEXAS INSTRUMENTS ]
