TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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Table 8-48. EMAC Interrupt Control (EMIC) Registers (continued)
HEX ADDRESS
02C8 101C
ACRONYM
C_MISC_EN
REGISTER NAME
Core n Misc Interrupt Enable Register, n = 0, 1 and 2
02C8 1040
C_RX_THRESH_STAT
Core n Receive Threshold Masked Interrupt Status Register, n = 0, 1
and 2
02C8 1044
02C8 1048
02C8 104C
C_RX_STAT
C_TX_STAT
Core n Receive Interrupt Masked Interrupt Status Register, n = 0, 1
and 2
Core n Transmit Interrupt Masked Interrupt Status Register, n = 0, 1
and 2
C_MISC_STAT
Core n Misc Interrupt Masked Interrupt Status Register, n = 0, 1 and
2
02C8 1070
02C8 1074
C_RX_IMAX
C_TX_IMAX
Core 0 Receive Interrupts Per Millisecond, n = 0, 1 and 2
Core 0 Transmit Interrupts Per Millisecond, n = 0, 1 and 2
8.12.3 EMAC Electrical Data/Timing (SGMII)
The TMS320TCI6488 Hardware Design Guide application report (literature number SPRAAG5) specifies a
complete EMAC anc SGMII interface solutions for the TCI6487/8 device as well as a list of compatible
EMAC and SGMII devices. TI has performed the simulation and system characterization to ensure all
EMAC and SGMII interface timings in this solution are met.
TI only supports designs that follow the board design guidelines outlined in the SPRAAG5
application report.
Table 8-49. Timing Requirements for SRIOSGMIIREFCLK(N|P)(1)
(see Figure 8-31)
NO.
PARAMETERS
MIN
MAX UNIT
1
tc(SRIOSGMIIREFCLK Cycle time, SRIOSGMIIREFCLK(N|P)
3.2
8
ns
)
2
3
4
5
tw(CLKH)
tw(CLKL)
tt(CLK)
Pulse duration, CLK(N|P) high
Pulse duration, CLK(N|P) low
Transition time, CLK(N|P)
0.4C
0.4C
50
ns
ns
ps
ps
1300
4
tj(CLK)
Period Jitter (RMS), CLK(N|P)
(1) C=1/SRIOSGMIIREFCLK(N|P)
1
4
2
SRIOSGMIIREFCLK(N|P)
3
4
Figure 8-31. SRIOSGMIIREFCLK(N|P) Timing
148
Peripheral Information and Electrical Specifications
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