TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
Table 8-44. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C8 0150
02C8 0154
02C8 0158
02C8 015C
02C8 0160
02C8 0164
02C8 0168
02C8 016C
02C8 0170
02C8 0174
02C8 0178 - 02C8 01CC
02C8 01D0
02C8 01D4
02C8 01D8
02C8 01DC
02C8 01E0
02C8 01E4
02C8 01E8
02C8 01EC
02C8 01F0 - 02C8 01FC
02C8 0200
02C8 0204
02C8 0208
02C8 020C
02C8 0210
02C8 0214
02C8 0218
02C8 021C
02C8 0220
02C8 0224
02C8 0228
02C8 022C
02C8 0230
02C8 0234
02C8 0238
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
ACRONYM
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFCONTROL
MACCONFIG
SOFTRESET
REGISTER NAME
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
Soft Reset Register
-
Reserved
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TRACETEST
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
RXPAUSE
TXPAUSE
Transmit Pause Timer Register
Reserved
-
RXGOODFRAMES
RXBCASTFRAMES
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Good Receive Frames Register
Broadcast Receive Frames Register
Multicast Receive Frames Register
Pause Receive Frames Register
Receive CRC Errors Register
RXALIGNCODEERRORS Receive Alignment/Code Errors Register
RXOVERSIZED
RXJABBER
Receive Oversized Frames Register
Receive Jabber Frames Register02C80220
Receive Undersized Frames Register
Receive Frame Fragments Register
Filtered Receive Frames Register
RXUNDERSIZED
RXFRAGMENTS
RXFILTERED
RXQOSFILTERED
RXOCTETS
Receive QOS Filtered Frames Register
Receive Octet Frames Register
TXGOODFRAMES
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
TXCOLLISION
Good Transmit Frames Register
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
144
Peripheral Information and Electrical Specifications
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