TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 8-44. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
02C8 028C
ACRONYM
FRAME65T127
REGISTER NAME
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
02C8 0500
-
Reserved
Reserved
-
MACADDRLO
MAC Address Low Bytes Register (used in Receive Address
Matching)
02C8 0504
MACADDRHI
MAC Address High Bytes Register (used in Receive Address
Matching)
02C8 0508
02C8 050C - 02C8 05FC
02C8 0600
MACINDEX
-
MAC Index Register
Reserved
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive t Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive t Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive t Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive t Channel 7 DMA Head Descriptor Pointer Register
02C8 0604
02C8 0608
02C8 060C
02C8 0610
02C8 0614
02C8 0618
02C8 061C
02C8 0620
02C8 0624
02C8 0628
02C8 062C
02C8 0630
02C8 0634
02C8 0638
02C8 063C
02C8 0640
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0644
02C8 0648
02C8 064C
02C8 0650
02C8 0654
02C8 0658
02C8 065C
TX1CP
TX2CP
TX3CP
TX4CP
TX5CP
TX6CP
TX7CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
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Peripheral Information and Electrical Specifications
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