TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
Figure 8-28. McBSP Timing
Table 8-43. Timing Requirements for FSR When GSYNC = 1
(see Figure 8-29)
NO.
MIN
4
MAX UNIT
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
4
CLKS
1
2
FSR External
CLKR/X
(No Need to Resync)
CLKR/X
(Needs to Resync)
Figure 8-29. FSR Timing When GSYNC = 1
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Peripheral Information and Electrical Specifications
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